1. Field of the Invention
The present invention relates to a solid-state image pickup element and a method of manufacturing the same, and an image pickup device including the same.
2. Description of the Related Art
In a CCD (Charge Coupled Device) solid-state image pickup element and a CMOS (Complementary Metal Oxide Semiconductor) solid-state image pickup element, it is known that crystal defects generated in a photodiode, and interface states generated in an interface between a light receiving portion formed in a silicon substrate, and an insulating layer overlying the light receiving portion cause a dark current.
FIG. 13A is a schematic cross sectional view showing a state in which an insulating layer is formed on a silicon layer having a photodiode formed therein, and FIG. 13B is an energy diagram of the insulating layer and the silicon layer shown in FIG. 13A. Thus, as shown in FIGS. 13A and 13B, interface states each indicated by a mark x are generated in an interface between the silicon layer 51 having the photodiode formed therein, and the insulating layer 52 overlying the silicon layer 51. Each of these interface states becomes a generation source of the dark current, and thus electrons each resulting from the interface are caused in the form of the dark current to flow into the photodiode PD.
Then, a so-called Hole Accumulation Diode (HAD) structure is adopted as a technique for suppressing the generation of the dark current. The HAD structure, for example, is described in Japanese Patent Laid-Open No. 2005-123280 (referred to as Patent Document 1 hereinafter).
FIG. 14A is a schematic cross sectional view explaining the case where a p+-type semiconductor region is formed to obtain the HAD structure, and FIG. 14B is an energy diagram of the silicon layer, the insulating layer, and a positive charge accumulation region formed between the silicon layer and the insulating layer. Specifically, as shown in FIGS. 14A and 14B, a p-type impurity is introduced into the vicinity of a surface of the silicon layer 51 to form the p+-type semiconductor region, and the resulting p+-type semiconductor region is made the positive charge accumulation region 53 for accumulating therein positive charges (holes).
The HAD structure in which the positive charge accumulation region 53 is formed in the interface between the silicon layer 51 and the insulating layer 52 is obtained in the manner as described above, whereby the photodiode is kept clear of the interface, thereby making it possible to suppress the generation of the dark current from the interface states each serving as the generation source.
In general, in forming the HAD structure, ions of B, BF2 or the like are implanted into the silicon layer at an annealing temperature, thereby forming the p+-type semiconductor region becoming the positive charge accumulation region 53 in the vicinity of the interface.
Also, for the purpose of realizing the proper diffusion and activation of the implanted impurity ions, it is essential to the existing ion implantation process to hold a high temperature for as long as possible.
However, holding the high temperature for a long time is not desirable from a viewpoint of sufficiently ensuring the characteristics and the like of the solid-state image pickup element.
In order to cope with this situation, as shown in FIGS. 15A and 15B, it is proposed that an insulating layer 55 containing therein negative fixed charges 54 is formed as the insulating layer formed so as to overlie the silicon layer 51 having the photodiode PD formed therein instead of forming the normal insulating layer 52. This structure, for example, is described in Japanese Patent Laid-Open No. 2008-306154 (referred to as Patent Document 2 hereinafter).
In this case, as shown in FIG. 15B, even when the impurity ions are not implanted into the silicon layer 51, the positive charge accumulation region 53 is formed in the vicinity of the interface between the silicon layer 51 and the insulating layer 55 by bending the energy band of the insulating layer 55, thereby allowing the positive charges (holes) to be accumulated in the positive charge accumulation region 53.
HfO2, ZrO2, Al2O3, TiO2, Ta2O5 or the like is given as the material for such an insulating layer 55 containing therein the negative fixed charges 54.